1. Field of the Invention
The present invention relates to a mask pattern forming method for use in the manufacture of semiconductor devices or the like, and more particularly to a pattern forming method capable of shortening a processing time, suppressing increase in data size and forming a micropattern, its program, and a semiconductor device manufacturing method which uses the program.
2. Description of the Related Art
Recent progress in semiconductor manufacturing technology has been very conspicuous, and semiconductors of a minimum processing size of 0.13 μm are now mass-produced. Such micronization has been realized by rapid progress of micropattern forming technology such as mask processing technology, lithography processing technology, and etching processing technology. In the era of sufficiently large pattern sizes, a mask pattern of the same shape as that of the pattern drawn by a designer was formed, and this mask pattern was transferred to a resist applied on a wafer by an exposing device, thereby enabling formation of a pattern as designed.
However, as the micronized pattern size has caused increase in the influence of diffraction of exposure light on a size on the wafer and a difficulty of a mask and wafer processing technology for accurately forming the micropattern, it is now difficult to form a pattern on the wafer as designed even when the same mask as that of a design pattern is used.
To improve fidelity of the design pattern, technologies called optical proximity correction (OPC) and process proximity correction (PPC) for forming a mask pattern to form a pattern identical to the design pattern on the wafer have been used.
The OPC and PPC technologies (referred to as PPC including the OPC, hereinafter) are largely classified into two methods. One is a method for defining a moving amount of an edge constituting the design pattern as a rule in accordance with a width of the design pattern, a most proximate distance between patterns, or the like, and moving the edge based on this rule (e.g., see Jpn. Pat. Appln. KOKAI Publication No. 2005-24903).
The other method is for setting an edge moving amount to be optimal so that a pattern identical to the design pattern can be formed on the wafer by using a lithography simulator capable of highly accurately predicting a diffracted light intensity distribution of diffracted light of the exposure light. Additionally, there has been proposed a correction method for realizing more accurate correction by combining these two methods.
As described above, micronization has brought about an essential necessity of much higher accuracy of OPC. Especially, a size fluctuation in an exposure shot which control of the exposure device or the process has been capable of suppressing to a predetermined size variance has become conspicuous. There is an urgent need not only to suppress such a fluctuation by making exposure device specifications more strict and a process control technology more accurate, but also to establish an OPC correction technology which reflects influences thereof. According to conventional OPC, correction can be made by presuming that the influences are all similar among shots. However, when the influences vary from shot to shot, it has been difficult to allocate different correction amounts to positions. Reasons are as follows.
First, in the case of OPC, areas having influences on a size of the pattern on the wafer are patterns alone present in several μm around the pattern. Thus, when pattern arrangements are completely identical within several μm, equal correction values are always allocated.
For this reason, a hierarchical structure originally owned by the design data can be effectively used. Even when identical layers (cells) are arranged in a plurality of shots, only by processing data of one cell, it is possible to obtain effects similar to those when data of the plurality of cells are processed, to greatly shorten a data processing time, and to suppress the amount of completed data small.
However, when the different correction values are allocated to the positions in the shots, the above effects cannot be obtained. In other words, as there is a need to allocate the different correction values in the shots, the hierarchy of the design data must be subject to roughly flat operation, greatly extending the data processing time and increasing the amount of data.
The above is especially conspicuous in a memory device (SRAM, DRAM, NAND, or NOR) having many repeated patterns. Obviously, there is a demand for establishment of a data processing method which uses a hierarchical structure of a design pattern as much as possible while allocating different correction values among shots to highly accurately correct a memory at high speed.